1. Field of the Invention
The present invention relates to an AD converting apparatus and an AD converting method.
2. Description of the Related Art
There is a case of converting a large number of analog signals into digital signals (AD conversion). In this case, it is not economically efficient to provide an AD converting apparatus for each analog signal. For this reason, it is considered to provide one AD converter for the plurality of analog signals and to carry out the AD conversion while switching the input analog signals.
A conventional AD converting apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-88723). FIG. 1 is a diagram showing a configuration of the conventional AD converting apparatus. The conventional AD converting apparatus is provided with a multiplexer 54, an AD converter 56, a result storing buffer 58, a CPU 60, a bus 62 and a controller 70. The multiplexer 54 selects one from a plurality of analog input terminals in accordance with an input terminal specification signal from the controller 70. The AD converting section 56 converts an analog signal of the analog input terminal selected by the multiplexer into a digital signal and stores a conversion result in the result storing buffer 58. The controller 70 outputs the input terminal specification signal to the multiplexer 54 in accordance with an AD conversion order that is arbitrarily specified.
The controller 70 has a channel specifying register 52. The conventional AD converting apparatus has a selection mode and a scan mode. For example, as shown in FIG. 2, when the channel specifying data to specify an analog input terminal “3” is set in the channel register 52 by the CPU 60 in the selection mode, the analog signal from the analog input channel corresponding to “3” is fixedly converted into the digital signal. Also, in the scan mode, all of the analog input channels are selected in order from the analog input channels specified by the channel specifying data held in the channel specifying register 52 of the controller 70, and the analog signal of the selected analog input channel is converted into the digital signal.
In the conventional AD converting apparatus, when the analog input channels “0 to 2” are specified, the analog signals from the analog input channels corresponding to “0”, “1” and “2” are converted into the digital signals in the selection mode. Thus, the AD converting section 56 is intermittently stopped, which makes it inefficient.
Also, in the conventional AD converting apparatus, even if a conversion cycle to be AD-converted is different for each analog signal, the conversion cycle cannot be changed for each analog signal. If the conversion cycle is arbitrarily changed, the CPU needs to receive an interruption and again to set a channel specifying data in the register. However, this implies that the AD conversion is not carried out until a new channel specifying data is set. A period until the interruption is received or a bus occupation of DMA is assumed, and a period while the AD converter is stopped is unstable. Thus, a time schedule cannot be set unless any circuit such as a timer that is periodically operated is used. Moreover, a limit of an assignment of the analog input channel and a load of a software process of CPU are generated.
For these reasons, the channel specifying data shown in FIG. 3 has been conventionally used so as to be able to freely set the analog input channel of the analog signal. In the channel specifying data, the lower four-bit specifies a start channel (analog input channel) for the AD conversion, and the higher four-bit specifies an end channel (analog input channel) for the AD conversion. For example, if the AD converting apparatus specifies the analog input channels “0 to 2”, the start channel is “0”, and the end channel is “2”. Through the usage of the foregoing channel specifying data, the analog signals of the channels within the specified range can be converted into the digital signals.
However, in the AD converting apparatus that uses the foregoing channel specifying data, if “0”, “2” and “4” are specified as the necessary analog input channels, the analog signals from the analog input channels corresponding to “0”, “2” and “4” are converted into the digital signals at the selection mode. Thus, the AD converting section is intermittently stopped, like the conventional AD converting apparatus in FIG. 1. Also, since the specifying method of the analog input channel is based on the range specification, only the necessary analog input channel cannot be selected.